1. Field of the Invention
The invention relates generally to a program counting circuit and a program word line voltage generating circuit in a flash memory device using the same. More particularly, the invention relates to a program counting circuit for generating a step pulse necessary in an increment step pulse program (ISPP) used in a NAND type flash memory device.
2. Description of the Prior Art
In nonvolatile semiconductor memory devices such as EEPROM (electrically erasable and programmable read only memory), flash memories, and the like, NOR type nonvolatile semiconductor memory devices in which a program operation for data is performed by injecting channel hot electrons (hereinafter called ‘CHE’) into a floating gate, has been widely used.
In the mentioned NOR type semiconductor nonvolatile memory devices, a high current is necessarily required upon the CHE data program. However, it is difficult to supply this current by the boosting circuit within the chip. In particular, in case that the power supply voltage is a low voltage, there is a problem that the boosting circuit is difficult to operate using a single power supply. Further, in the NOR type nonvolatile semiconductor memory devices, the data program operation can be performed for only eight memory cells at a time in a byte unit, i.e., in parallel, due to current limit. Thus, this becomes a limit in increasing the program speed.
Recently, due to limitation of the NOR type semiconductor nonvolatile memory devices, NAND type nonvolatile semiconductor memory devices (hereinafter called ‘NAND type flash memory’) having a high memory capacity and that can be high-integrated, in which the data program is performed by injecting the electrons into the floating gate using a Fowler-Nordheim (hereinafter called ‘F-N’) tunneling phenomenon, have been proposed.
The NAND type flash memory has advantages that the operating current can relatively easily generates using the boosting circuit within the chip and the memory can be operated using this single current since the current is low upon the data program. With these advantages, in the NAND type flash memory, the data program operation can be performed for the memory cells connected to a selected word line, in a page unit, i.e., in batch. The program speed can be thus increased.
In the mentioned NAND type flash memory, however, if irregularity of the program characteristic caused by process irregularity, etc. is large in the data program operation, difference in the program speed between the memory cells connected to the selected word line is increased, and the repeated number of the program and verify operations is increased. Thus, there is a problem that the program speed is reduced. In the NAND type flash memory, there exists difference in the program time of about 2 order between the memory cells within the selected word line. In a conventional mode in which program pulses of the same pulse voltage values and the same pulse time widths are simply repeatedly applied, it is required that the number of the program and verify be performed about by 100 times. In this case, time taken to switch the voltage of the program operation and the verify read operation is significantly longer than time taken to apply the program voltage. An actual program speed is thus reduced. In order to solve this program, it is required that the data program operation be performed by inhibiting the number of the program and verify operations to 10 times by maximum.
However, in the mode in which the program pulses are simply repeatedly applied, it is required that the program pulse of a little high pulse voltage be applied in order to execute the data program operation. In this case, the memory cell for which the program speed is the highest is over erased. Due to this, there is a problem that irregularity of a program threshold voltage (Vt) (hereinafter called ‘threshold voltage’) is increased.
In order to solve this problem, a new method of programming the NAND type flash memory by which the number of the program and verify operation can be prohibited without increasing the irregularity of the Vt, was disclosed in a document, 95 ISSCC entitled “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme (ISPP scheme) p. 128˜”.
In the ISPP scheme disclosed in the above document, when the program operation is repeatedly performed, the data program operation is performed so that the difference in the program voltages is gradually increased as the number of the program operation is increased, by setting a program word line voltage (i.e., high voltage applied to the selected word line) to a variable voltage value in which it is gradually increased as the number of the program operation is increased, and reference bit line voltage (i.e. voltage applied to the reference bit line) to a constant voltage value regardless of the number of the program operation.
In the data program operation by this ISPP scheme, even though the program Vt is raised as the program operation of the memory cell is performed due to increased number of the program operation, decrease in the potential of the floating gate is compensated for through the program word line voltage that is gradually increased. Thus, the electric field applied to the tunnel oxide film of the memory cell is always constantly kept.
As such, in the program operation of the ISPP scheme, it is required that the program word line voltage in which the voltage value that is step by step changed in a direction that the number of the program operation is increased, be generated. For this, a program word line voltage generating circuit is required. This circuit includes a program counting circuit.
In the conventional program counting circuit, data (i.e., power supply voltage or ground voltage) for setting an initial counting value of a flip-flop is not received from the outside, or data is received through a plurality of transistors if the data is received from the outside. Accordingly, it is difficult to control the number of the program and verify operations using the conventional program counting circuit. Even though control the number of the program and verify operations is controlled, several bus lines and the plurality of the transistors are required. Thus, there is a problem that the entire structure of the program word line voltage generating circuit is complicated.